FS N5850 / N8500 Series (Trident 2+ / Tomahawk)
The FS N5850 and N8500 series cover three distinct Broadcom ASICs from the 16 nm / 40 nm transitional era, all sharing a 16 MB total buffer figure but with different internal architectures.
Models
| Model | ASIC | Ports | Capacity | Buffer |
|---|---|---|---|---|
| N5850-48S6Q | BCM56864 (Trident 2+) | 48x 10G SFP+, 6x 40G QSFP+ | 720 Gbps | 16 MB unified |
| N8500-32C | BCM56960 (Tomahawk) | 32x 100G QSFP28 | 6.4 Tbps | 16 MB (4 pipes × 4 MB) |
| N8500-48B6C | BCM56967 (Tomahawk+) | 48x 25G SFP28, 6x 100G QSFP28 | 3.6 Tbps | 16 MB unified |
Buffer Architecture
N5850-48S6Q — BCM56864 (Trident 2+)
The Trident 2+ (BCM56864) carries a 16 MB unified shared buffer. This is an incremental improvement over the Trident 2's 12 MB, retaining the dynamic shared pool architecture. All 16 MB is accessible to any port experiencing congestion.
N8500-32C — BCM56960 (Tomahawk)
The original Tomahawk (BCM56960) carries 16 MB of total buffer, but it is not a unified pool. The chip's internal architecture divides the data path into four parallel pipelines, each with its own 4 MB buffer slice serving 8 front-panel ports. A congested group of 8 ports can only access its own 4 MB slice — even if the other three slices are idle. This is an important operational distinction from unified-buffer chips. The N8500-32C inherits this constraint directly.
N8500-48B6C — BCM56967 (Tomahawk+)
The Tomahawk+ (BCM56967) retains the 16 MB total buffer but addresses the segmented-pipe limitation of the original Tomahawk with a more unified memory management architecture. The N8500-48B6C uses this chip for its 25G/100G density.
References
- FS N5850-48S6Q Product Page
- FS N8500-32C Product Page
- FS N8500-48B6C Product Page
- UCSC Warner — FS N8500 Analysis
See Also
- Broadcom Trident II Architecture — predecessor context
- Broadcom Trident 3 Architecture — successor with unified 32 MB
- Back to the main buffer table