Packet Buffer Reference

Broadcom Trident II (BCM56850 / BCM56854)

Broadcom's follow-on to the Trident+ is the StrataXGS Trident II:

Announced in 2012, it became available in production volumes in November 2013.

Buffer Architecture

In common with the Trident+, all packet buffers are on the switch chip. Where the Trident+ has 9 MB of packet buffers, the Trident II has 12 MB. The memory is segmented into dedicated per-port buffers and a dynamic shared pool that can be loaned to any queue and port that needs it. Most of the memory is in the shared pool. For more information, see the listing for the Arista 7050X.

While we have not seen switches implemented with more than a single Trident+ chip, the Trident II can be used in larger switches with crossbar connections between switching elements. The Arista 7250 is an example.

New Features

One of the new features introduced with the Trident II is support for VXLAN — specifically NVGRE (Network Virtualization General Route Encapsulation). This stimulated a range of switches with data center features built on Trident II silicon.

The BCM56850 has 128 SERDES to provision 32 quad ports. If used for 1RU switches with 10 Gb/s ports, 48 SERDES would be stranded with no place to connect — sufficient reason to have the BCM56854 variant.

Trident II+ (BCM56860) — April 2015

The Trident was followed by the Trident+; thus it is with the Trident II. The Trident II+ (BCM56860) was announced in April 2015.

Key features:

See Also